Primary Processor-Based VM-Execution Controls bit 28 = Use MSR bitmaps
set to 0 = all guest executions of RDMSR / WRMSR cause vm exits
set to 1 = you need to enable corresponding bit in MSR bitmap to intercept MSR you like.
Because you didn't intercept RDMSR, I'm only guessing that your bit 28 of the above control was 1 and corresponding bit in MSR bitmap was 0. Remember MSR bitmap VMCS field is PA, not VA, but to change any bit you need to have it mapped into some VA.
Which MSR you want to watch? You can access some guest MSRs by executing RDMSR in root mode, some guest MSRs are in VMCS so you get them by vmread, some are / are not in VMCS according settings of some control bits (save IA32_EFER VM-exit control and so on).
There are also MSR exit store address and VM entry load address, but that should not lead into missing RDMSR vm exit.
hypervisor-based solutions developer (Intel, AMD)